< hvic > M81738FP 1200v high voltage half bridge driver preliminary publication date : jan 2012 pin configuration (top view) features floating supply voltage up to 1200v low quiescent power supply current separate sink and source current output up to 1a (typ) active miller effect clamp nmos with sink current up to 1a (typ) input noise filters (hin,lin,fo_rst,fo) over-current detection and output shutdown high side under voltage lockout fo pin which can input and output fault signals to communicate with controllers and synchronize the shut down with other phases active clamp (power supply surge clamp) 24pin ssop-lead package block diagram outline:24p2q applications power mosfet and igbt gate driver for inverter or general purpose. 1 nc hin lin fo_rst cin gnd fo vcc lpout lnout1 lnout2 vno nc nc vb hpout hnout1 hnout2 vs nc nc nc nc nc description M81738FP is 1200v high voltage power mosfet and igbt module driver for half bridge applications. vreg1 logic filter uv+por filter filter noise filter delay por vregvcc levelshift oneshot pulse delay vregvcc levelshift filter interlock protection logic vregvcc levelshift vreg1 vreg vreg hv levelshift active clamp active clamp vcc gnd hin lin cin fo_rst v b hpou t hnou t hnou v s v cc lpou lnou lnou v no fo
1200v high voltage half bridge driver M81738FP preliminary publication date : jan 2012 2 v -0.5v cc +0.5 cin input voltage v cin v/ns 50 v s - gnd allowable offset voltage slew rate dv s /dt v -0.5v cc +0.5 fo input/output voltage v fo v v cc -24v cc +0.5 power ground v no -40125 junction temperature tj c/w 90 on our standard pcb junction-ambient air thermal resistance rth(j-a) mw/ c 11.1 ta R 25 c ,on our standard pcb linear derating factor k ? w 1.11 ta= 25 c ,on our standard pcb package power dissipation pd v -0.5v cc +0.5 hin, lin, fo_rst logic input voltage v in v v no -0.5v cc +0.5 low side output voltage v lo v -0.524 low side fixed supply voltage v cc absolute maximum ratings absolute maximum ratings indicate limitation beyond which destr uction of device may occur. all voltage parameters are absolute voltage reference to gnd unless otherwise specified. symbol parameter test conditions raitings unit v b high side floating supply absolute voltage -0.51224 v v s high side floating supply offset voltage v b -24 v b +0.5 v v bs high side floating supply voltage v bs =v b -v s -0.524 v v ho high side output voltage v s -0.5 v b +0.5 v topr operation temperature -40100 tstg storage temperature -40150 v v cc - v no low side output voltage v lo v v cc - 0 hin, lin, fo_rst logic input voltage v in v 5 - -0.5 power ground v no v 5 - 0 cin input voltage v cin v v cc - 0 fo input/output voltage v fo v 20 15 13.5 low side fixed supply voltage v cc v v s +20 - v s high side output voltage v ho v 20 15 13.5 v bs =v b -v s high side floating supply voltage v bs v 900 - -5 v bs > 13.5v high side floating supply offset voltage v s v v s +20 v s +15 v s +13.5 high side floating supply absolute voltage v b max. typ. min. unit limits test conditions parameter symbol recommended operating conditions for proper operation the device should be used within the re commended conditions. all voltage parameters are absolute voltages referenced to gnd unless otherwise specified. thermal derating factor characteristic 0 0.2 0.4 0.6 0.8 1 1.2 0 25 50 75 100 125 150 ambience temperature () package power dissipation pd (w)
1200v high voltage half bridge driver M81738FP preliminary publication date : jan 2012 3 note: if hvic is working in high noise environment, it is recommended to connect a 1nf ceramic capacitor (c fo ) to fo pin. m81019fp dc bus voltage rshunt vout vno dc- vb vcc rboot dboot cboot dc+ vs hpout hnout1 hnout lpout lnout1 lnout gnd cin r cin c cin fo hin lin fo_rst mcu/dsp controller other phases 15v hout lout 5v~15v r gon r gon r goff r goff r fo c fo M81738FP typical connection
1200v high voltage half bridge driver M81738FP preliminary publication date : jan 2012 4 ns 400 180 -20 tdlh(lo)-tdhl(ho) delay matching, high side turn-off and low side turn-on ? tdhl ns 500 200 80 hin off-pulse ns 500 200 80 lin on-pulse ns 500 200 80 lin off-pulse ns 500 200 80 fo_rst on-pulse ns 500 200 80 fo off-pulse ns - 400 - v in =0v active miller clamp nmos filter time tv no2 v 9.0 7.6 6.0 v in =0v low side active miller clamp nmos input threshold voltage v lno2 v 5.0 3.4 2.0 v in =0v high side active miller clamp nmos input threshold voltage v hno2 ?? - 15 - i o = -1a, r ol2 = v o /i o active miller clamp nmos output low level on resistance r ol2 a - -1 - hnout2(lnout2) = 15v, v in = 0v, pw Q 10 ? s active miller clamp nmos output low level short circuit pulsed current i ol2 a - -1 - hnout1(lnout1) = 15v, v in = 0v, pw Q 10 ? s output low level short circuit pulsed current i ol1 a - 1 - hpout(lpout) = 0v, v in = 5v, pw Q 10 ? s output high level short circuit pulsed current i oh ? s 1.70 1.19 0.90 lpout short to lnout1 and lnout2, cl = 1nf low side turn-off propagation delay tdhl(lo) ? s 1.90 1.39 1.00 lpout short to lnout1 and lnout2, cl = 1nf low side turn-on propagation delay tdlh(lo) ns 300 80 -100 tdlh(ho)-tdhl(lo) delay matching, high side turn-on and low side turn-off ? tdlh v 12.1 11.3 10.5 v bs supply uv trip voltage v bsuvt v 0.95 - - i fo =1ma low level fo output voltage v olfo note: typ. is not specified. v - - 24 v cc Cgnd, v b -v s active clamp voltage v clamp ns 80 40 10 cl = 1nf output turn-off fall time tf ns 80 40 10 cl = 1nf output turn-on rise time tr ? s 1.80 1.21 0.90 hpout short to hnout1 and hnout2, cl = 1nf high side turn-off propagation delay tdhl(ho) ? s 1.80 1.27 1.00 hpout short to hnout1 and hnout2, cl = 1nf high side turn-on propagation delay tdlh(ho) ?? - 15 - i o = -1a, r ol1 = v o /i o output low level on resistance r ol1 ?? - 15 - i o = 1a, r oh = (v oh -v o )/i o output high leve l on resistance r oh v 7.5 5.5 4.0 por trip voltage v por v 0.60 0.5 0.40 cin trip voltage v cin ? s 16 8 4 v bs supply uv filter time tv bsuv v 0.8 0.5 0.2 v bsuvh = v bsuvr -v bsuvt v bs supply uv hysteresis voltage v bsuvh v 11.6 10.8 10.0 v bs supply uv reset voltage v bsuvr v 2.1 1.5 0.6 low level fo input threshold voltage v ilfo v 4.0 3.0 2.2 high level fo input threshold voltage v ihfo ns 500 200 80 hin on-pulse input signals filter time tfilter ma 0.01 0.00 0.00 v in =0v low level input bias current i il ma 1.4 1.0 0.6 v in =5v high level input bias current i ih v 2.1 1.5 0.6 hin, lin, fo_rst low level input threshold voltage v il v 4.0 3.0 2.2 hin, lin, fo_rst high level input threshold voltage v ih v 0.5 - - i o = 0a, hnout1, lnout1 low level output voltage v ol v - - 14.5 i o = 0a, hpout, lpout high level output voltage v oh ma 1.5 1.0 - hin = lin = 0v v cc quiescent supply current i cc ma 0.8 0.5 - hin = lin = 0v v bs quiescent supply current i bs ? a 10 - - v b = v s = 1200v high side leakage current i fs max. typ. min. unit limits test conditions parameter symbol electrical characteristics (ta=25 c,v cc =v bs (=v b -v s )=15v, unless otherwise specified)
1200v high voltage half bridge driver M81738FP preliminary publication date : jan 2012 5 function table (q: keep previous status) v bs power reset is tripping when lin = h h h l h l - l l h x v bs power reset h l l h l - l l l x v cc power reset h l l l x - x x x x output shuts down when fo = l - l l h x l x x x x cin not tripping when lin = l h q q h x - h x l x cin tripping when lin = h l l l h x - h x h x interlock active h q q h h - l l h h h l h h h - l l l h h h l h h - l l h l h l l h h - l l l l behavioral status fo (output) lout hout v cc / por v bs / uv?por fo (input) cin fo_rst lin hin note1 :?l? status of v bs /uv indicates a high side uv condition; ?l? status of v cc /por indicates a v cc power reset condition. note 2 : in the case of both input signals (hin and lin) are ?h?, output signals (hout and lout) keep previous status. note 3 : x (hin) : l h or h l. other : h or l. note 4 : output signal (hout) is triggered by the edge of input signal. functional description 1. input/output timing diagram 50% 10% 90% 90% 10% 50% 10% 90% 90% 10% hin lin ho lo tr tf S tdlh S tdhl tdhl(lo) tdlh(lo) td hl(ho) tdlh(ho) tr tf
1200v high voltage half bridge driver M81738FP preliminary publication date : jan 2012 6 2. input interlock timing diagram 3. short circuit protection timing diagram when an over-current is detected by exceedi ng the threshold at the cin and lin is at high level at the same time, the short cir cuit protection will get active and shutdown the ou tputs while fo will issue a low level (i ndicating a fault signal). the fault outp ut latch is reset by a high level signal at fo_rst pin and then fo will retu rn to high level while the output of the driver will respond to the following active input signal. when the input signals (hin/lin) are high level at the same time, the outputs (hout/lout) keep their previous status. but if signals (hin/lin) are going to high level simultaneously, h in signals will get active and cause hout to enter ?h? status. note1 :the minimum input pulse width at hi n/lin should be to more than 500ns (because of hin/lin input noise filter circuit). note2 :if a high-high status of input si gnals (hin/lin) is ended with only one in put signal entering low level and another sti ll being in high level, the output will enter high-low status after the delay match time (not shown in the figure above). note3 :delay times between input and output signals are not shown in the figure above. note1 : delay times between input and output signals are not shown in the figure above. note2 : the minimum fo_rst pulse width should be more than 500ns (because of fo_r st input filter circuit). hin lin hout lout hin lin cin fo_rst hout lout fo
1200v high voltage half bridge driver M81738FP preliminary publication date : jan 2012 4. fo input timing diagram when fo is pulled down to low level in case the fo of other phases becomes low level (fault happ ened) or the mcu/dsp sets fo to low level, the outputs (hout, lout) of the driver will be shut down. as soon as fo goes high again, the output will respond to the following active input signal. 7 note1 :delay times between input and output signals are not shown in the figure above. note2 :the minimum fo pulse width should be more t han ns (because of fo input filter circuit). 5. low side v cc supply power reset sequence when the v cc supply voltage is lower than power reset trip voltage, the power reset gets active and the outputs (lout) become ?l?. as soon as the v cc supply voltage goes higher than the power rese t trip voltage, the outputs will respond to the following active input signals. note1 :delay times between input and output signals are not shown in the figure above. hin lin hout lout fo hin lin hout lout v cc vpor voltage
1200v high voltage half bridge driver M81738FP preliminary publication date : jan 2012 8 6. high side v bs supply under voltage lockout sequence when v bs supply voltage drops below the v bs supply uv trip voltage and the durati on in this status exceeds the v bs supply uv filter time, the output of the high side is locked. as soon as the v bs supply voltage rises above the v bs supply uv reset voltage, the output will respond to the following active hin signal. note1 :delay times between input and output signals are not shown in the figure above. 7. power start-up sequence at power supply start-up the following sequence is recommended when bootstrap supply topology is used. note : if two power supply are used for supplying v cc and v bs individually, it is recommended to set v cc first and then set v bs . (1). apply v cc . (2). make sure that fo is at high level. (3). set lin to high level and hin to low level so that bootstrap capacitor could be charged. (4). set lin to low level. hin lin hout lout v bs v bs supply uv hysteresis voltage v bs supply uv filter time v bs uvt v bs uvr v bs uvr v cc hin lin lout fo
1200v high voltage half bridge driver M81738FP preliminary publication date : jan 2012 9 9 8. active miller effect clamp nmos output timing diagram the structure of the output driv er stage is shown in following figure. this ci rcuit structure employs a solution for the proble m of the miller current through cres in igbt switching applications. inst ead of driving the igbt gate to a negative voltage to increase t he safety margin, this circuit structure uses a nmos to establish a low impedance path to prevent the self-t urn-on due to the paras itic miller capacitor in power switches. when hin/lin is at low level and the voltage of the vout (igbt gate voltage) is below active miller effect clamp nmos input threshold voltage, the active miller effect clamp nmos is being turned on and opens a low resistive path for the miller current through cres. active miller effect clamp nmos keeps turn-on if t w does not exceed active miller clamp nmos filter time c res c ies v bs/ v cc v s /vno v in =0 (from hin/lin) v out high dv/dt active miller clamp nmos v in v pg v n1g vout v n2g tw n1 off n1 on n1 off p1 on p1 off p1 on n2 off n2 on n2 off active miller clamp nmos input threshold voltage
1200v high voltage half bridge driver M81738FP preliminary publication date : jan 2012 10 package outline internal diode clamp circuits for input and output pins gnd hin lin cin fo_rst hpout hnout1 hnout2 v cc lpout lnout1 lnout2 v no v no v cc gnd v cc vs gnd v cc v b v b fo gnd v cc
1200v high voltage half bridge driver M81738FP preliminary publication date : jan 2012 11 main revision for this edition points pages revision date no.
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